NVM Technology Atlas

e− / h+

Blue indicates electrons; red indicates holes. Arrows follow carriers.

I

Green arrows show conventional current, opposite to electrons and aligned with holes.

Bias

Only operating roles are shown; terminal voltages and pulse specifications are not supplied.

Scale

Geometry and dielectrics are enlarged for readability, not a process layout.

FG / Q−

FG has no DC terminal. Q− follows the historical p+ charge model, including localized negative ionic charge.

UV*

The 2021 brief lists UV erase. Normal OTP lacks electrical erase; UV access depends on implementation and package.

Do not draw oxide rupture, a permanent filament or nMOS CHE; do not invent voltages or universal current p+ doping. SL, SG/WL, BL and NW; FG floats. SG is separate from FG; capacitive BL coupling is not a DC connection.

e− / h+

Blue indicates electrons; red indicates holes. Arrows follow carriers.

I

Green arrows show conventional current, opposite to electrons and aligned with holes.

Bias

Only operating roles are shown; terminal voltages and pulse specifications are not supplied.

Scale

Geometry and dielectrics are enlarged for readability, not a process layout.

FG / Q−

FG has no DC terminal. Q− follows the historical p+ charge model, including localized negative ionic charge.

UV*

The 2021 brief lists UV erase. Normal OTP lacks electrical erase; UV access depends on implementation and package.

Do not draw oxide rupture, a permanent filament or nMOS CHE; do not invent voltages or universal current p+ doping. SL, SG/WL, BL and NW; FG floats. SG is separate from FG; capacitive BL coupling is not a DC connection.

e− / h+

Blue indicates electrons; red indicates holes. Arrows follow carriers.

I

Green arrows show conventional current, opposite to electrons and aligned with holes.

Bias

Only operating roles are shown; terminal voltages and pulse specifications are not supplied.

Scale

Geometry and dielectrics are enlarged for readability, not a process layout.

FG / Q−

FG has no DC terminal. Q− follows the historical p+ charge model, including localized negative ionic charge.

UV*

The 2021 brief lists UV erase. Normal OTP lacks electrical erase; UV access depends on implementation and package.

Do not draw oxide rupture, a permanent filament or nMOS CHE; do not invent voltages or universal current p+ doping. SL, SG/WL, BL and NW; FG floats. SG is separate from FG; capacitive BL coupling is not a DC connection.

e− / h+

Blue indicates electrons; red indicates holes. Arrows follow carriers.

I

Green arrows show conventional current, opposite to electrons and aligned with holes.

Bias

Only operating roles are shown; terminal voltages and pulse specifications are not supplied.

Scale

Geometry and dielectrics are enlarged for readability, not a process layout.

DT / 3T

DT describes direct tunneling through a shorter effective barrier after defect generation. SEL/REG are published functions; the related patent is not a verified current NeoFuse netlist.

No thick metallic short or FG storage; the damaged high-k/interfacial sublayer of current advanced processes is unverified. Antifuse gate AF, underlying Si, selection/regulation controls and BL; storage dielectric lies between AF and Si, not in the selector oxide.

e− / h+

Blue indicates electrons; red indicates holes. Arrows follow carriers.

I

Green arrows show conventional current, opposite to electrons and aligned with holes.

Bias

Only operating roles are shown; terminal voltages and pulse specifications are not supplied.

Scale

Geometry and dielectrics are enlarged for readability, not a process layout.

DT / 3T

DT describes direct tunneling through a shorter effective barrier after defect generation. SEL/REG are published functions; the related patent is not a verified current NeoFuse netlist.

No thick metallic short or FG storage; the damaged high-k/interfacial sublayer of current advanced processes is unverified. Antifuse gate AF, underlying Si, selection/regulation controls and BL; storage dielectric lies between AF and Si, not in the selector oxide.

e− / h+

Blue indicates electrons; red indicates holes. Arrows follow carriers.

I

Green arrows show conventional current, opposite to electrons and aligned with holes.

Bias

Only operating roles are shown; terminal voltages and pulse specifications are not supplied.

Scale

Geometry and dielectrics are enlarged for readability, not a process layout.

DT / 3T

DT describes direct tunneling through a shorter effective barrier after defect generation. SEL/REG are published functions; the related patent is not a verified current NeoFuse netlist.

No thick metallic short or FG storage; the damaged high-k/interfacial sublayer of current advanced processes is unverified. Antifuse gate AF, underlying Si, selection/regulation controls and BL; storage dielectric lies between AF and Si, not in the selector oxide.

e−

Blue dots are mobile electrons and blue arrows follow electron flow; they are not charge retained inside the gate.

I

Green denotes conventional current, opposite to electrons. The illustrated branch fixes positive gate bias and a low BL.

OTP

The local orange path indicates conductive oxide state; normal operation has no electrical erase.

I_L / I_H

Short/long bars illustrate low/high read-current comparison, not measured values or fixed logic coding.

Geometry

Historical public-source functional reconstruction, not a scale section or current layout; terminal biases are not process operating specifications.

M0 / M1

M0 stores and M1 selects. No sense output absent from the original is added at their internal node.

Uses Figure 1 explicitly named XPM in the 2007 patent and the 2012 product announcement. Later self-sensing, latch and 3T drawings are excluded. Positive WLP and low BL define this nMOS teaching branch; read uses lower stress without implementation voltages. Acquisition announcements establish portfolio continuity; current 1T/2T or advanced-process articles do not prove this section is retained at every node.

e−

Blue dots are mobile electrons and blue arrows follow electron flow; they are not charge retained inside the gate.

I

Green denotes conventional current, opposite to electrons. The illustrated branch fixes positive gate bias and a low BL.

OTP

The local orange path indicates conductive oxide state; normal operation has no electrical erase.

I_L / I_H

Short/long bars illustrate low/high read-current comparison, not measured values or fixed logic coding.

Geometry

Historical public-source functional reconstruction, not a scale section or current layout; terminal biases are not process operating specifications.

M0 / M1

M0 stores and M1 selects. No sense output absent from the original is added at their internal node.

Uses Figure 1 explicitly named XPM in the 2007 patent and the 2012 product announcement. Later self-sensing, latch and 3T drawings are excluded. Positive WLP and low BL define this nMOS teaching branch; read uses lower stress without implementation voltages. Acquisition announcements establish portfolio continuity; current 1T/2T or advanced-process articles do not prove this section is retained at every node.

e−

Blue dots are mobile electrons and blue arrows follow electron flow; they are not charge retained inside the gate.

I

Green denotes conventional current, opposite to electrons. The illustrated branch fixes positive gate bias and a low BL.

OTP

The local orange path indicates conductive oxide state; normal operation has no electrical erase.

I_L / I_H

Short/long bars illustrate low/high read-current comparison, not measured values or fixed logic coding.

Geometry

Historical public-source functional reconstruction, not a scale section or current layout; terminal biases are not process operating specifications.

M0 / M1

M0 stores and M1 selects. No sense output absent from the original is added at their internal node.

Uses Figure 1 explicitly named XPM in the 2007 patent and the 2012 product announcement. Later self-sensing, latch and 3T drawings are excluded. Positive WLP and low BL define this nMOS teaching branch; read uses lower stress without implementation voltages. Acquisition announcements establish portfolio continuity; current 1T/2T or advanced-process articles do not prove this section is retained at every node.

e−

Blue dots are mobile electrons and blue arrows follow electron flow; they are not charge retained inside the gate.

I

Green denotes conventional current, opposite to electrons. The illustrated branch fixes positive gate bias and a low BL.

OTP

The local orange path indicates conductive oxide state; normal operation has no electrical erase.

I_L / I_H

Short/long bars illustrate low/high read-current comparison, not measured values or fixed logic coding.

Geometry

Historical public-source functional reconstruction, not a scale section or current layout; terminal biases are not process operating specifications.

WL / BL

WL connects to one poly gate and BL to the sole N+ diffusion. Only the thin core oxide is shown breaking down. Horizontal carrier paths are offset for readability from the under-gate surface channel; they do not indicate conduction through the p-type bulk.

The section follows the product article’s n-type structure. Positive WL and low BL define the teaching bias from which directions are inferred. Detailed voltages from the historical p-type patent example are excluded. Split channel means neither two separate gates nor a floating gate. Acquisition announcements establish portfolio continuity; current 1T/2T or advanced-process articles do not prove this section is retained at every node.

e−

Blue dots are mobile electrons and blue arrows follow electron flow; they are not charge retained inside the gate.

I

Green denotes conventional current, opposite to electrons. The illustrated branch fixes positive gate bias and a low BL.

OTP

The local orange path indicates conductive oxide state; normal operation has no electrical erase.

I_L / I_H

Short/long bars illustrate low/high read-current comparison, not measured values or fixed logic coding.

Geometry

Historical public-source functional reconstruction, not a scale section or current layout; terminal biases are not process operating specifications.

WL / BL

WL connects to one poly gate and BL to the sole N+ diffusion. Only the thin core oxide is shown breaking down. Horizontal carrier paths are offset for readability from the under-gate surface channel; they do not indicate conduction through the p-type bulk.

The section follows the product article’s n-type structure. Positive WL and low BL define the teaching bias from which directions are inferred. Detailed voltages from the historical p-type patent example are excluded. Split channel means neither two separate gates nor a floating gate. Acquisition announcements establish portfolio continuity; current 1T/2T or advanced-process articles do not prove this section is retained at every node.

e−

Blue dots are mobile electrons and blue arrows follow electron flow; they are not charge retained inside the gate.

I

Green denotes conventional current, opposite to electrons. The illustrated branch fixes positive gate bias and a low BL.

OTP

The local orange path indicates conductive oxide state; normal operation has no electrical erase.

I_L / I_H

Short/long bars illustrate low/high read-current comparison, not measured values or fixed logic coding.

Geometry

Historical public-source functional reconstruction, not a scale section or current layout; terminal biases are not process operating specifications.

WL / BL

WL connects to one poly gate and BL to the sole N+ diffusion. Only the thin core oxide is shown breaking down. Horizontal carrier paths are offset for readability from the under-gate surface channel; they do not indicate conduction through the p-type bulk.

The section follows the product article’s n-type structure. Positive WL and low BL define the teaching bias from which directions are inferred. Detailed voltages from the historical p-type patent example are excluded. Split channel means neither two separate gates nor a floating gate. Acquisition announcements establish portfolio continuity; current 1T/2T or advanced-process articles do not prove this section is retained at every node.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

BD

The orange polyline marks a conduction path after dielectric breakdown.

If the target macro is eFuse or floating-gate OTP, open a separate unit; do not reuse this drawing.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

BD

The orange polyline marks a conduction path after dielectric breakdown.

If the target macro is eFuse or floating-gate OTP, open a separate unit; do not reuse this drawing.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

BD

The orange polyline marks a conduction path after dielectric breakdown.

If the target macro is eFuse or floating-gate OTP, open a separate unit; do not reuse this drawing.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

Fuse

The orange path marks a high-R fuse after electromigration, not an explosive gap.

I-fuse is neither AntiFuse nor conventional explosive eFuse.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

Fuse

The orange path marks a high-R fuse after electromigration, not an explosive gap.

I-fuse is neither AntiFuse nor conventional explosive eFuse.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

Fuse

The orange path marks a high-R fuse after electromigration, not an explosive gap.

I-fuse is neither AntiFuse nor conventional explosive eFuse.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

BD

The orange polyline marks a conduction path after dielectric breakdown.

The product name is LEE Fuse ZA; a page typo of LEE Flash ZA does not change the mechanism class.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

BD

The orange polyline marks a conduction path after dielectric breakdown.

The product name is LEE Fuse ZA; a page typo of LEE Flash ZA does not change the mechanism class.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

BD

The orange polyline marks a conduction path after dielectric breakdown.

The product name is LEE Fuse ZA; a page typo of LEE Flash ZA does not change the mechanism class.

e− / h+

Blue indicates electrons; red indicates holes. Arrows follow carriers.

I

Green arrows show conventional current, opposite to electrons and aligned with holes.

Bias

Only operating roles are shown; terminal voltages and pulse specifications are not supplied.

Scale

Geometry and dielectrics are enlarged for readability, not a process layout.

FG / Q−

FG is an isolated floating gate; blue minus signs indicate stored electrons.

C / T / S / R

Coupling, tunneling, selection and read roles; not official pins or a fixed device count. T groups the MOS tunneling regions used by the operations, without asserting one physical terminal. No charge-to-ON/OFF polarity is assigned.

Exclude the historical CHE/FN branch; do not assert exactly two physical capacitors or that more electrons always mean ON. C, T, R and S denote coupling, tunneling, read-channel and selection functions, not official pins. Shared FG has no external supply connection.

e− / h+

Blue indicates electrons; red indicates holes. Arrows follow carriers.

I

Green arrows show conventional current, opposite to electrons and aligned with holes.

Bias

Only operating roles are shown; terminal voltages and pulse specifications are not supplied.

Scale

Geometry and dielectrics are enlarged for readability, not a process layout.

FG / Q−

FG is an isolated floating gate; blue minus signs indicate stored electrons.

C / T / S / R

Coupling, tunneling, selection and read roles; not official pins or a fixed device count. T groups the MOS tunneling regions used by the operations, without asserting one physical terminal. No charge-to-ON/OFF polarity is assigned.

Exclude the historical CHE/FN branch; do not assert exactly two physical capacitors or that more electrons always mean ON. C, T, R and S denote coupling, tunneling, read-channel and selection functions, not official pins. Shared FG has no external supply connection.

e− / h+

Blue indicates electrons; red indicates holes. Arrows follow carriers.

I

Green arrows show conventional current, opposite to electrons and aligned with holes.

Bias

Only operating roles are shown; terminal voltages and pulse specifications are not supplied.

Scale

Geometry and dielectrics are enlarged for readability, not a process layout.

FG / Q−

FG is an isolated floating gate; blue minus signs indicate stored electrons.

C / T / S / R

Coupling, tunneling, selection and read roles; not official pins or a fixed device count. T groups the MOS tunneling regions used by the operations, without asserting one physical terminal. No charge-to-ON/OFF polarity is assigned.

Exclude the historical CHE/FN branch; do not assert exactly two physical capacitors or that more electrons always mean ON. C, T, R and S denote coupling, tunneling, read-channel and selection functions, not official pins. Shared FG has no external supply connection.

e− / h+

Blue indicates electrons; red indicates holes. Arrows follow carriers.

I

Green arrows show conventional current, opposite to electrons and aligned with holes.

Bias

Only operating roles are shown; terminal voltages and pulse specifications are not supplied.

Scale

Geometry and dielectrics are enlarged for readability, not a process layout.

FG / Q−

FG is an isolated floating gate; blue minus signs indicate stored electrons.

EG / SL / SG / BL / NW

EG is the published erase function; the remaining labels are pMOS teaching terminals. EG geometry/materials are not a current layout; its arrow expresses the FG-to-EG FN path.

Do not draw injected holes in FG or substitute conventional nMOS CHE; historical edge n+ EG requires separate attribution. SL, SG, BL and well contact follow the pMOS concept; EG is a published erase terminal. Current EG doping, geometry and voltages are not fully disclosed. These are teaching terminals, not an official pin table.

e− / h+

Blue indicates electrons; red indicates holes. Arrows follow carriers.

I

Green arrows show conventional current, opposite to electrons and aligned with holes.

Bias

Only operating roles are shown; terminal voltages and pulse specifications are not supplied.

Scale

Geometry and dielectrics are enlarged for readability, not a process layout.

FG / Q−

FG is an isolated floating gate; blue minus signs indicate stored electrons.

EG / SL / SG / BL / NW

EG is the published erase function; the remaining labels are pMOS teaching terminals. EG geometry/materials are not a current layout; its arrow expresses the FG-to-EG FN path.

Do not draw injected holes in FG or substitute conventional nMOS CHE; historical edge n+ EG requires separate attribution. SL, SG, BL and well contact follow the pMOS concept; EG is a published erase terminal. Current EG doping, geometry and voltages are not fully disclosed. These are teaching terminals, not an official pin table.

e− / h+

Blue indicates electrons; red indicates holes. Arrows follow carriers.

I

Green arrows show conventional current, opposite to electrons and aligned with holes.

Bias

Only operating roles are shown; terminal voltages and pulse specifications are not supplied.

Scale

Geometry and dielectrics are enlarged for readability, not a process layout.

FG / Q−

FG is an isolated floating gate; blue minus signs indicate stored electrons.

EG / SL / SG / BL / NW

EG is the published erase function; the remaining labels are pMOS teaching terminals. EG geometry/materials are not a current layout; its arrow expresses the FG-to-EG FN path.

Do not draw injected holes in FG or substitute conventional nMOS CHE; historical edge n+ EG requires separate attribution. SL, SG, BL and well contact follow the pMOS concept; EG is a published erase terminal. Current EG doping, geometry and voltages are not fully disclosed. These are teaching terminals, not an official pin table.

FG / Cc / CG

FG is a floating gate with no DC terminal. Cc is a functional coupling capacitor; CG is its external control terminal.

N+ / p / B

N+ denotes model source/drain regions, p the nMOS body, and B its terminal. Concentrations, well layout and dimensions are unspecified.

S / D*

S is the model source. D* is the selected high-field end and model drain, not a ymtp macro-pin mapping.

e− / h+

Blue e− and arrows represent electrons; red h+ and arrows represent holes. Particle counts and animation speed are qualitative.

I / I_R / Iref

Green I is conventional current, opposite to electron motion. I_R is read current and Iref is the sensing reference.

BBT / BBHH

BBT is band-to-band tunneling in silicon. BBHH uses the resulting holes for hot-hole injection; crossing the dielectric is a subsequent step.

Vth / QFG

Vth is the effective nMOS threshold and QFG is FG charge. The actual product defines biases, sensing margins and logic encoding.

An independent CHI / BBHH teaching model; cited sources do not establish BBHH in current YMC ymtp products. It uses an equivalent 1T1C and qualitative directions rather than a current version-specific cross-section or bias table. Independent original research supports BBHH physics; YMC FN/DAHHI patent variants retain their distinct mechanisms.

FG / Cc / CG

FG is a floating gate with no DC terminal. Cc is a functional coupling capacitor; CG is its external control terminal.

N+ / p / B

N+ denotes model source/drain regions, p the nMOS body, and B its terminal. Concentrations, well layout and dimensions are unspecified.

S / D*

S is the model source. D* is the selected high-field end and model drain, not a ymtp macro-pin mapping.

e− / h+

Blue e− and arrows represent electrons; red h+ and arrows represent holes. Particle counts and animation speed are qualitative.

I / I_R / Iref

Green I is conventional current, opposite to electron motion. I_R is read current and Iref is the sensing reference.

BBT / BBHH

BBT is band-to-band tunneling in silicon. BBHH uses the resulting holes for hot-hole injection; crossing the dielectric is a subsequent step.

Vth / QFG

Vth is the effective nMOS threshold and QFG is FG charge. The actual product defines biases, sensing margins and logic encoding.

An independent CHI / BBHH teaching model; cited sources do not establish BBHH in current YMC ymtp products. It uses an equivalent 1T1C and qualitative directions rather than a current version-specific cross-section or bias table. Independent original research supports BBHH physics; YMC FN/DAHHI patent variants retain their distinct mechanisms.

FG / Cc / CG

FG is a floating gate with no DC terminal. Cc is a functional coupling capacitor; CG is its external control terminal.

N+ / p / B

N+ denotes model source/drain regions, p the nMOS body, and B its terminal. Concentrations, well layout and dimensions are unspecified.

S / D*

S is the model source. D* is the selected high-field end and model drain, not a ymtp macro-pin mapping.

e− / h+

Blue e− and arrows represent electrons; red h+ and arrows represent holes. Particle counts and animation speed are qualitative.

I / I_R / Iref

Green I is conventional current, opposite to electron motion. I_R is read current and Iref is the sensing reference.

BBT / BBHH

BBT is band-to-band tunneling in silicon. BBHH uses the resulting holes for hot-hole injection; crossing the dielectric is a subsequent step.

Vth / QFG

Vth is the effective nMOS threshold and QFG is FG charge. The actual product defines biases, sensing margins and logic encoding.

An independent CHI / BBHH teaching model; cited sources do not establish BBHH in current YMC ymtp products. It uses an equivalent 1T1C and qualitative directions rather than a current version-specific cross-section or bias table. Independent original research supports BBHH physics; YMC FN/DAHHI patent variants retain their distinct mechanisms.

FG / e−

The brown FG is dielectric-isolated and has no external DC connection. Blue minus signs denote electrons; their count is qualitative.

C / T_P / T_E

C denotes capacitive coupling. T_P and T_E denote program/erase tunnel counterparts. Reusing the enlarged window does not assert one physical terminal or a fixed device count.

Si / Dielectric

Blue-gray regions represent silicon functions; pale yellow represents insulating dielectric. Doping, thickness, relative size and actual layout are unspecified.

e− / E

Blue open arrows show electron motion. Brown arrows show the tunnel-region electric field E, opposite to electron force. Program adds FG electrons; erase removes them in this convention. No official 0/1 coding is assigned.

A / B / I_R

A and B are functional read terminals, not official pins. The green arrow denotes conventional sensing current for A above B. MOS polarity is unspecified, so no carrier direction or fixed charge-to-ON/OFF relation is assigned.

2009 AEON / FN–FN

The model follows the named 2009 AEON company article. Business transfers and Synopsys branding form a separate timeline and do not prove identical internal cells across generations.

T_P/T_E are operating roles and must not be assumed to be one physical pin. MOS polarity, device count, wells, voltages and logic coding are unspecified. Do not substitute early Impinj hot-electron patents or the internal cell of every current Synopsys MTP product.

FG / e−

The brown FG is dielectric-isolated and has no external DC connection. Blue minus signs denote electrons; their count is qualitative.

C / T_P / T_E

C denotes capacitive coupling. T_P and T_E denote program/erase tunnel counterparts. Reusing the enlarged window does not assert one physical terminal or a fixed device count.

Si / Dielectric

Blue-gray regions represent silicon functions; pale yellow represents insulating dielectric. Doping, thickness, relative size and actual layout are unspecified.

e− / E

Blue open arrows show electron motion. Brown arrows show the tunnel-region electric field E, opposite to electron force. Program adds FG electrons; erase removes them in this convention. No official 0/1 coding is assigned.

A / B / I_R

A and B are functional read terminals, not official pins. The green arrow denotes conventional sensing current for A above B. MOS polarity is unspecified, so no carrier direction or fixed charge-to-ON/OFF relation is assigned.

2009 AEON / FN–FN

The model follows the named 2009 AEON company article. Business transfers and Synopsys branding form a separate timeline and do not prove identical internal cells across generations.

T_P/T_E are operating roles and must not be assumed to be one physical pin. MOS polarity, device count, wells, voltages and logic coding are unspecified. Do not substitute early Impinj hot-electron patents or the internal cell of every current Synopsys MTP product.

FG / e−

The brown FG is dielectric-isolated and has no external DC connection. Blue minus signs denote electrons; their count is qualitative.

C / T_P / T_E

C denotes capacitive coupling. T_P and T_E denote program/erase tunnel counterparts. Reusing the enlarged window does not assert one physical terminal or a fixed device count.

Si / Dielectric

Blue-gray regions represent silicon functions; pale yellow represents insulating dielectric. Doping, thickness, relative size and actual layout are unspecified.

e− / E

Blue open arrows show electron motion. Brown arrows show the tunnel-region electric field E, opposite to electron force. Program adds FG electrons; erase removes them in this convention. No official 0/1 coding is assigned.

A / B / I_R

A and B are functional read terminals, not official pins. The green arrow denotes conventional sensing current for A above B. MOS polarity is unspecified, so no carrier direction or fixed charge-to-ON/OFF relation is assigned.

2009 AEON / FN–FN

The model follows the named 2009 AEON company article. Business transfers and Synopsys branding form a separate timeline and do not prove identical internal cells across generations.

T_P/T_E are operating roles and must not be assumed to be one physical pin. MOS polarity, device count, wells, voltages and logic coding are unspecified. Do not substitute early Impinj hot-electron patents or the internal cell of every current Synopsys MTP product.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

e−

Blue dots denote electrons; the count is qualitative.

SuperMTP is marked under development on the vendor page and is not used in this unit’s operation drawings.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

e−

Blue dots denote electrons; the count is qualitative.

SuperMTP is marked under development on the vendor page and is not used in this unit’s operation drawings.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

e−

Blue dots denote electrons; the count is qualitative.

SuperMTP is marked under development on the vendor page and is not used in this unit’s operation drawings.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

h+

Red dots denote hot holes; the count is qualitative.

e−

Blue dots denote hot electrons; the count is qualitative.

TwinBit is not drawn as PermSRAM spacer trapping, and bias numbers are unspecified.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

h+

Red dots denote hot holes; the count is qualitative.

e−

Blue dots denote hot electrons; the count is qualitative.

TwinBit is not drawn as PermSRAM spacer trapping, and bias numbers are unspecified.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

h+

Red dots denote hot holes; the count is qualitative.

e−

Blue dots denote hot electrons; the count is qualitative.

TwinBit is not drawn as PermSRAM spacer trapping, and bias numbers are unspecified.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

e−

Blue dots denote electrons; the count is qualitative.

Cycle-count copy on the page conflicts with itself; no count is treated as a guarantee.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

e−

Blue dots denote electrons; the count is qualitative.

Cycle-count copy on the page conflicts with itself; no count is treated as a guarantee.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

e−

Blue dots denote electrons; the count is qualitative.

Cycle-count copy on the page conflicts with itself; no count is treated as a guarantee.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

SiN

Terracotta marks the nitride trap layer; thickness is unpublished.

A BCD narrative cannot be extrapolated to every logic node.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

SiN

Terracotta marks the nitride trap layer; thickness is unpublished.

A BCD narrative cannot be extrapolated to every logic node.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

SiN

Terracotta marks the nitride trap layer; thickness is unpublished.

A BCD narrative cannot be extrapolated to every logic node.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

SiN

Terracotta marks the nitride trap layer; thickness is unpublished.

The vendor marks ongoing development; this drawing teaches only the published structural principle.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

SiN

Terracotta marks the nitride trap layer; thickness is unpublished.

The vendor marks ongoing development; this drawing teaches only the published structural principle.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

SiN

Terracotta marks the nitride trap layer; thickness is unpublished.

The vendor marks ongoing development; this drawing teaches only the published structural principle.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

e−

Blue dots denote electrons; the count is qualitative.

The process range is a licensing narrative, not proof of one production node.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

e−

Blue dots denote electrons; the count is qualitative.

The process range is a licensing narrative, not proof of one production node.

Dielectric

Pale yellow marks a dielectric; thickness and material are unspecified.

Channel / Well

Blue-gray marks a silicon channel or well function, not a metrology cross-section.

Bias / I

Green arrows denote bias or conventional current direction.

e−

Blue dots denote electrons; the count is qualitative.

The process range is a licensing narrative, not proof of one production node.

FL / RL

Free/reference layers; arrows are moments, not particle flow

Ic / e−

Orange solid line: conventional current; blue dashed electrons flow oppositely

A / B; BL* / SL*

A/B define drawing terminals; asterisks mean the actual layer-to-array-line mapping is not asserted

WL; P / AP

Word-line selection; parallel low resistance / antiparallel high resistance

τSTT

Spin-transfer torque; the intermediate arrow only illustrates reversal

This reconstructs the public Numem IP architecture for teaching. Current sources do not disclose materials, thicknesses, vertical order, write-terminal polarity, or logic encoding. Directions A/B mean two calibrated opposite drives. The 2019 forced-current read is not a specification for every product.

FL / RL

Free/reference layers; arrows are moments, not particle flow

Ic / e−

Orange solid line: conventional current; blue dashed electrons flow oppositely

A / B; BL* / SL*

A/B define drawing terminals; asterisks mean the actual layer-to-array-line mapping is not asserted

WL; P / AP

Word-line selection; parallel low resistance / antiparallel high resistance

τSTT

Spin-transfer torque; the intermediate arrow only illustrates reversal

This reconstructs the public Numem IP architecture for teaching. Current sources do not disclose materials, thicknesses, vertical order, write-terminal polarity, or logic encoding. Directions A/B mean two calibrated opposite drives. The 2019 forced-current read is not a specification for every product.

FL / RL

Free/reference layers; arrows are moments, not particle flow

Ic / e−

Orange solid line: conventional current; blue dashed electrons flow oppositely

A / B; BL* / SL*

A/B define drawing terminals; asterisks mean the actual layer-to-array-line mapping is not asserted

WL; P / AP

Word-line selection; parallel low resistance / antiparallel high resistance

τSTT

Spin-transfer torque; the intermediate arrow only illustrates reversal

This reconstructs the public Numem IP architecture for teaching. Current sources do not disclose materials, thicknesses, vertical order, write-terminal polarity, or logic encoding. Directions A/B mean two calibrated opposite drives. The 2019 forced-current read is not a specification for every product.

FL / RL

Free/reference layers; arrows are moments, not particle flow

Ic / e−

Orange solid line: conventional current; blue dashed electrons flow oppositely

A / B; BL* / SL*

A/B define drawing terminals; asterisks mean the actual layer-to-array-line mapping is not asserted

WL; P / AP

Word-line selection; parallel low resistance / antiparallel high resistance

τSTT

Spin-transfer torque; the intermediate arrow only illustrates reversal

Polarity follows this paper: positive Ic flows RL-to-FL and writes P; reverse writes AP. This sign convention and recipe are not universal to MRAM. Obtain BL/SL layer mapping and values from the PDK; undisclosed barrier material and exact thicknesses are omitted.

FL / RL

Free/reference layers; arrows are moments, not particle flow

Ic / e−

Orange solid line: conventional current; blue dashed electrons flow oppositely

A / B; BL* / SL*

A/B define drawing terminals; asterisks mean the actual layer-to-array-line mapping is not asserted

WL; P / AP

Word-line selection; parallel low resistance / antiparallel high resistance

τSTT

Spin-transfer torque; the intermediate arrow only illustrates reversal

Polarity follows this paper: positive Ic flows RL-to-FL and writes P; reverse writes AP. This sign convention and recipe are not universal to MRAM. Obtain BL/SL layer mapping and values from the PDK; undisclosed barrier material and exact thicknesses are omitted.

FL / RL

Free/reference layers; arrows are moments, not particle flow

Ic / e−

Orange solid line: conventional current; blue dashed electrons flow oppositely

A / B; BL* / SL*

A/B define drawing terminals; asterisks mean the actual layer-to-array-line mapping is not asserted

WL; P / AP

Word-line selection; parallel low resistance / antiparallel high resistance

τSTT

Spin-transfer torque; the intermediate arrow only illustrates reversal

Polarity follows this paper: positive Ic flows RL-to-FL and writes P; reverse writes AP. This sign convention and recipe are not universal to MRAM. Obtain BL/SL layer mapping and values from the PDK; undisclosed barrier material and exact thicknesses are omitted.

Ti / SiOx / TiN

Top electrode/switching oxide/bottom electrode, limited to the public CEA example

O²− / VO

Filled blue circles are oxygen ions; open orange circles are vacancies, with no silver metal

TE / BE; WL

Top/bottom electrodes and select gate; TE bias is referenced to BE

Ic / e−

Conventional current and electrons flow oppositely; neither denotes oxygen motion

This is the public Weebit/CEA-Leti/Silvaco research model, not a product recipe for every foundry node. SET: positive TE, O²− toward Ti. RESET: negative TE, oxygen returns into SiOx and recombines near the BE-side path. Forming is an initial condition, not every write.

Ti / SiOx / TiN

Top electrode/switching oxide/bottom electrode, limited to the public CEA example

O²− / VO

Filled blue circles are oxygen ions; open orange circles are vacancies, with no silver metal

TE / BE; WL

Top/bottom electrodes and select gate; TE bias is referenced to BE

Ic / e−

Conventional current and electrons flow oppositely; neither denotes oxygen motion

This is the public Weebit/CEA-Leti/Silvaco research model, not a product recipe for every foundry node. SET: positive TE, O²− toward Ti. RESET: negative TE, oxygen returns into SiOx and recombines near the BE-side path. Forming is an initial condition, not every write.

Ti / SiOx / TiN

Top electrode/switching oxide/bottom electrode, limited to the public CEA example

O²− / VO

Filled blue circles are oxygen ions; open orange circles are vacancies, with no silver metal

TE / BE; WL

Top/bottom electrodes and select gate; TE bias is referenced to BE

Ic / e−

Conventional current and electrons flow oppositely; neither denotes oxygen motion

This is the public Weebit/CEA-Leti/Silvaco research model, not a product recipe for every foundry node. SET: positive TE, O²− toward Ti. RESET: negative TE, oxygen returns into SiOx and recombines near the BE-side path. Forming is an initial condition, not every write.

Ag / a-Si / p+ poly-Si

Silver top electrode/amorphous silicon/selected lower buffer-contact embodiment

Ag

Purple region and dots denote metal region/particles without asserting each charge state

TE / BE; WL

Top/bottom electrodes and select gate; 1T1R integration has a separate manufacturer source

Ic / e−

Conventional current opposes electron motion; electrons may tunnel between neighboring particles

This is a published patent embodiment associated with historical embedded IP, not proof of current macro recipes or newly licensable nodes in 2026. The patent describes metal particles and interparticle tunneling; the path is not equated to a solid silver bridge or generic cathode-nucleated ECM.

Ag / a-Si / p+ poly-Si

Silver top electrode/amorphous silicon/selected lower buffer-contact embodiment

Ag

Purple region and dots denote metal region/particles without asserting each charge state

TE / BE; WL

Top/bottom electrodes and select gate; 1T1R integration has a separate manufacturer source

Ic / e−

Conventional current opposes electron motion; electrons may tunnel between neighboring particles

This is a published patent embodiment associated with historical embedded IP, not proof of current macro recipes or newly licensable nodes in 2026. The patent describes metal particles and interparticle tunneling; the path is not equated to a solid silver bridge or generic cathode-nucleated ECM.

Ag / a-Si / p+ poly-Si

Silver top electrode/amorphous silicon/selected lower buffer-contact embodiment

Ag

Purple region and dots denote metal region/particles without asserting each charge state

TE / BE; WL

Top/bottom electrodes and select gate; 1T1R integration has a separate manufacturer source

Ic / e−

Conventional current opposes electron motion; electrons may tunnel between neighboring particles

This is a published patent embodiment associated with historical embedded IP, not proof of current macro recipes or newly licensable nodes in 2026. The patent describes metal particles and interparticle tunneling; the path is not equated to a solid silver bridge or generic cathode-nucleated ECM.